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ms81v04160 dual fifo (262,214-word x 8-bits) x 2 general description the ms81v04160 is a single-chip 4mb fifo functionally composed of two oki 2mb fifo (first-in first-out) memories which were designed for 256k x 8-bit high-speed asynchronous read/write operation. the read clocks and the write clocks of each of the 2mb fifo memories are connected in common. the ms81v04160, functionally compatible with oki's 2mb fifo memory (msm51v8222a), can be used as a x16 configuration fifo. the ms81v04160 is a field memory for wide or low end use in general commodity tvs and vtrs exclusively and is not designed for high end use in professional graphics systems, which require long term picture storage, data storage, medical use and other storage systems. the ms81v04160 provides independent control clocks to support asynchronous read and write operations. different clock rates are also supported, which allow alternate data rates between write and read data streams. the ms81v04160 provides high speed fifo (first-in first-out) operation without external refreshing: ms81v04160 refreshes its dram storage cells automatically, so that it appears fully static to the users. moreover, fully static type memory cells and decoders for serial access enable the refresh free serial access operation, so that serial read and/or write control clock can be halted high or low for any duration as long as the power is on. internal conflicts of memory access and refreshing operations are prevented by special arbitration logic. the ms81v04160s function is simple, and similar to a digital delay device whose delay-bit- length is easily set by reset timing. the delay length and the number of read delay clocks between write and read, is determined by externally controlled write and read reset timings. additional sram serial registers, or line buffers for the initial access of 256 x 16-bit enable high speed first-bit-access with no clock delay just after the write or read reset timings. additionally, the ms81v04160 has a write mask function or input enable function (ie), and read- data skipping function or output enable function (oe). the differences between write enable (we) and input enable (ie), and between read enable (re) and output enable (oe) are that we and re can stop serial write/read address increments, but ie and oe cannot stop the increment, when write/read clocking is continuously applied to ms81v04160. the input enable (ie) function allows the user to write into selected locations of the memory only, leaving the rest of the memory contents unchanged. this facilitates data processing to display a picture in picture on a tv screen. 1 oki semiconductor revision1 1999.4.15
2 ms81v04160 oki semiconductor -25 -30 tac 23ns 30ns tswc tsrc icc1 80ma 80ma icc2 (mode2 ="l") parameter symbol ms81v04160-xxtb access time read/write 25ns 30ns cycle time operation current standby current 3ma 3ma features 512 rows x 512 columns x 8 bits x2 fast fifo(first-in first-out)operation :25ns cycle time self refresh(no refresh control is required) high speed asynchronous serial access read/write cycle time 25ns/30ns access time 22ns/25ns variable length delay bit (600 to 262215) write mask function (output enable control) cascading capability by mode setting single power supply:3.3v p 10% package: 100-pin plastic tqfp(tqfp 100-p-1414-0.50-k)(product:ms81v04160-xxtb) xx indicates speed rank.
3 ms81v04160 oki semiconductor pin configuration (top view) note: the same power supply voltage must be provided to every vcc pin,and the same gnd voltage level must be provided to every vss pin. pin name pin name swck srck we1 we2 re1 re2 ie1 ie2 oe1 oe2 rstw1 rstw2 rstr1 rstr2 di 10-17 di 20-27 do 10-17 do 20-27 mode1,2,3 nc vc c vs s port2 data input port2 data output no connection ground(0v) port2 input inable port2 output inable port2 reset write port2 reset read function serial read clock port2 write inable port2 read inable port1 data input port1 data output mode input power supply(3.3v) port1 input inable port1 output inable port1 reset write port1 reset read function serial write clock port1 write inable port1 read inable 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 100 pin tqfp top view vcc do 20 do 21 vss do 22 do 23 do 24 do 25 vss do 26 do 27 vcc srck vcc do 17 do 16 vss do 15 do 14 do 13 do 12 vss do 11 do 10 vcc nc di 23 vss di 24 di 25 di 26 di 27 nc vss vss vcc vcc swck vcc vcc vss vss nc di 17 di 16 di 15 di 14 vss di 13 nc nc vss vss nc oe2 re2 rstr2 vcc nc mode1 nc vss nc vcc nc vss vcc vss we2 ie2 rstw2 di 20 di 21 di 22 nc nc vss vss nc oe1 re1 rstr1 vcc mode3 mode2 nc vss nc vcc nc vss vcc vss we1 ie1 rstw1 di 10 di 11 di 12 nc
4 ms81v04160 oki semiconductor block diagram - 256k ( q 8) memory array 512 word serial read register ( q 8) read line buffer low-half ( q 8) read line buffer high-half ( q 8) write line buffer low-half ( q 8) write line buffer high-half ( q 8) 512 word serial write register ( q 8) 256 ( q 8) 256 ( q 8) 256 ( q 8) 256 ( q 8) serial read controller re2 rstr2 srck we2 rstw2 swck 71 word sub-register ( q 8) data-in buffer ( q 8) data-out buffer ( q 8) do ( q 8) di ( q 8) read/write and refresh controller ie2 71 word sub-register ( q 8) controller serial write decoder oe2 clock oscillator vbb generator mode1,2,3 - 256k ( q 8) memory array 512 word serial read register ( q 8) read line buffer low-half ( q 8) read line buffer high-half ( q 8) write line buffer low-half ( q 8) write line buffer high-half ( q 8) 512 word serial write register ( q 8) 256 ( q 8) 256 ( q 8) 256 ( q 8) 256 ( q 8) serial read controller re1 rstr1 srck we1 rstw1 swck 71 word sub-register ( q 8) data-in buffer ( q 8) data-out buffer ( q 8) do ( q 8) di ( q 8) read/write and refresh controller ie1 71 word sub-register ( q 8) decoder oe1 serial write controller
5 ms81v04160 oki semiconductor data inputs: (din 10 - 17) these pins are used for serial data inputs. write reset: rstw1 the first positive transition of swck after rstw becomes high resets the write address pointers to zero. rstw1 setup and hold times are referenced to the rising edge of swck. because the write reset function is solely controlled by the swck rising edge after the high level of rstw, the states of we1 and ie1 are ignored in the write reset cycle. before rstw1 may be brought high again for a further reset operation, it must be low for at least two swck cycles. write enable: we1 we1 is used for data write enable/disable control. we1 high level enables the input, and we1 lowlevel disables the input and holds the internal write address pointer. there are no we1 disabletime (low) and we1 enable time (high) restrictions, because the ms8104160 is in fully static operation as long as the power is on. note that we1 setup and hold times are referenced to the rising edge of swck. input enable: ie1 ie1 is used to enable/disable writing into memory. ie1 high level enables writing. the internal write address pointer is always incremented by cycling swck regardless of the ie1 level. note that ie1 setup and hold times are referenced to the rising edge of swck. data out: (dout 0 - 11) these pins are used for serial data outputs. read reset: rstr1 the first positive transition of srck after rstr1 becomes high resets the read address pointers to zero. rstr1 setup and hold times are referenced to the rising edge of srck. because the read reset function is solely controlled by the srck rising edge after the high level of rstr, the states of re1 and oe1 are ignored in the read reset cycle. before rstr may be brought high again for a further reset operation, it must be low for at least *two srck cycles. read enable: re1 the function of re1 is to gate of the srck clock for incrementing the read pointer. when re1 is high before the rising edge of srck, the read pointer is incremented. when re1 is low, the read pointer is not incremented. re1 setup times (trens and trdss) and re1 hold times (trenh and trdsh) are referenced to the rising edge of the srck clock. output enable: oe1 oe1 is used to enable/disable the outputs. oe1 high level enables the outputs. the internal read address pointer is always incremented by cycling srck regardless of the oe1 level. note that oe1 setup and hold times are referenced to the rising edge of srck. pin description
6 ms81v04160 oki semiconductor serial write clock: swck the swck latches the input data on chip when we1, 2 is high, and also increments the internal write address pointer. data-in setup time tds, and hold time tdh are referenced to the rising edge of swck. serial read clock: srck data is shifted out of the data registers. it is triggered by the rising edge of srck when re1, 2 is highduring a read operation. the srck input increments the internal read address pointer when re1,2 is high. the three-state output buffer provides direct ttl compatibility (no pullup resistor required). data out is the same polarity as data in. the output becomes valid after the access time interval tac that begins with the rising edge of srck. *there are no output valid time restriction on ms8104160. data input: (din 20-27) these pins are used for serial data inputs. write reset: rstw2 the first positive transition of swck after rstw becomes high resets the write address pointers to zero. rstw2 setup and hold times are referenced to the rising edge of swck. because the write reset function is solely controlled by the swck rising edge after the high level of rstw2, the states of we2 and ie2 are ignored in the write reset cycle. before rstw2 may be brought high again for a further reset operation, it must be low for at least two swck cycles. write enable: we2 we is used for data write enable/disable control. we2 high level enables the input, and we2 lowlevel disables the input and holds the internal write address pointer. there are no we2 disabletime (low) and we2 enable time (high) restrictions, because the ms8104160 is in fully static operation as long as the power is on. note that we2 setup and hold times are referenced to the rising edge of swck. input enable: ie2 ie2 is used to enable/disable writing into memory. ie2 high level enables writing. the internal write address pointer is always incremented by cycling swck regardless of the ie2 level. note that ie2 setup and hold times are referenced to the rising edge of swck. data out : dout 20 C 27 these pins are used for serial data outputs. read reset: rstr2 the first positive transition of srck after rstr2 becomes high resets the read address pointers to zero. rstr2 setup and hold times are referenced to the rising edge of srck. because the read reset function is solely controlled by the srck rising edge after the high level of rstr2, the states of re2 and oe2 are ignored in the read reset cycle. before rstr2 may be brought high again for a further reset operation, it must be low for at least *two srck cycles.
7 ms81v04160 oki semiconductor output enable: oe2 oe2 is used to enable/disable the outputs. oe2 high level enables the outputs. the internal read address pointer is always incremented by cycling srck regardless of the oe2 level. note that oe2 setup and hold times are referenced to the rising edge of srck. mode setting: mode1 the cascade/non cascade select pin. setting the mode1 pin to the vcc level configures this memory device as cascade type and setting the pin to the vss level configures this memory device as non cascade. during memory operation, the pin must be permanentry connected to vcc or vss. if a mode1 level is changed during memory operation, memory data is not guaranteed. note: cascade/non cascade when mode1 is set to the vss level, memory accessing starts in the cycle in which the control signals are input (non cascade type). when mode1 is set to the vcc level, memory accessing starts in the cycle subsequent to the cycle in which the control signals are input (cascade type). this type is used for consecutive memory accessing. mode2 setting: mode2 mode2 selects whether the control input signals are enabled at a high level or a low level. setting mode2 to the vcc level enables the control input signals at a low level and setting mode2 to the vss level enables the control input signals at a high level. mode setting: mode3 the boost control pin for data-out buffer. for the ms8104160, the mode3 pin should be permanentry connected to the vss level.
8 ms81v04160 oki semiconductor electrical characteristics absolute maximum ratings symbol condition rating input output voltage v t -1.0 to 4.6 output current i os 50 power dissipation p d 1 operating temperature t opr storage temperature t stg -55 to 150 parameter at ta = 25 o c, v ss ta = 25 o c ta =25 o c 0 to 70 unit ma w o c o c v parameter symbol min. typ. max. unit power supply voltage v cc 3.0 3.3 3.6 v power supply voltage v ss 0 0 0 v input high voltage v ih 2.4 v cc v cc + 0.3 v input low voltage v il -0.3 0 0.8 v recommended operating conditions parameter symbol condition min. max. unit input leadkage current i li 0 < v i < v cc , other pins tested at v=0v -10 10 ua output leadkage current i lo 0 < v o < v cc -10 10 ua output h level voltage v oh i oh = -1 ma 2.4 - v output l level voltage v ol i ol = 2 ma - 0.4 v operating current i cc1 minimum cycle time, output open - 80 ma i cc2a mode2=l - 3 i cc2b mode2=h - 10 dc characteristics capacitance parameter symbol max. unit input capacitance (d in ,swck,srck,rstw,rstr,we,re,ie,oe) c i 7 pf outnput capacitance (d out ) c o 7 pf (ta = 25 o c , f = 1 mhz) standby current input pin = v ih / v il ma
9 ms81v04160 oki semiconductor ac characteristics ( vcc = 3.0 - 3.6v,ta = 0 to 70 o c ) parameter symbol unit min. max. access time from srck t ac 30 ns dout hold time from srck t ddck - ns dout enable time from srck t deck 30 ns swck "h" pulse width t wswh 20 ns swck "l" pulse width t wswl 20 ns input time data setup t ds ns input data hold time t dh ns we enable setup time t wens ns we enable hold time t wenh ns we disable setup time t wdss ns we disable hold time t wdsh ns ie enable setup time t iens ns ie enable hold time t ienh ns ie disable setup time t idss ns ie disable hold time t idsh ns we "h" pulse width t wweh ns we "l" pulse width t wwel ns ie "h" pulse width t wieh ns ie "l" pulse width t wiel ns rstw setup time t rstws ns rstw hold time t rstwh ns srck "h" pulse width t wsrh ns srck "l" pulse width t wsrl ns re enable setup time t rens ns re enable hold time t renh ns re disable setup time t rdss ns re disable hold time t rdsh ns oe enable setup time t oens ns oe enable hold time t oenh ns oe disable setup time t odss ns oe disable hold time t odsh ns re "h" pulse width t wreh ns re "l" pulse width t wrel ns oe "h" pulse width t woeh ns oe "l" pulse width t woel ns rstr setup time t rstrs ns rstr hold time t rstrh ns swck cycle time t swc ns srck cycle time t src - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ns transition time (rise and fall) t t - 23 6- 623 15 - 15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 30 - 6 6 30 ns min. max. ms81v04160-25 ms81v04160-30 3 5 5 5 5 5 (7) 5 5 5 5 5 5 5 3 15 15 3 5 3 5 3 5 3 5 5 5 5 5 3 10 25 25 3 5 5 5 5 5 5 5 5 3 10 20 20 3 5 3 5 3 5 3 5 3 30 30 3 5 (7) 5 (7) 5 (7) 10 10 10 10 10 10 10 10 10 10
10 ms81v04160 oki semiconductor notes: 1. input signal reference levels for the parameter measurement are v ih = 3.0 v and v il = 0 v. the transition time t t is defined to be a transition time that signal transfers between v ih = 3.0 v and v il = 0 v. 2. ac measurements assume t t = 3 ns. 3. read address must have more than a 600 address delay than write address in every cycle when asynchronous read/write is performed. 4. read must have more than a 600 address delay than write in order to read the data written in a current series of write cycles which has been started at last write reset cycle: this is called "new data read". when read has less than a 70 address delay than write, the read data are the data written in a previous series of write cycles which had been written before at last write reset cycle: this is called "old data read". 5. when the read address delay is between more than 71 and less than 599 or more than 262,214, read data will be undetermined. however, normal write is achieved in this address condition. 6. outputs are measured with a load equivalent to 1 ttl load and 30 pf. output reference levels are v oh = 1.5 v and v ol = 1.5 v. 7. ( ): mode2=vcc
11 ms81v04160 oki semiconductor write operation cycle (mode2=vss) the write operation is controlled by seven control signals, swck, rstw1, rstw2, we1, we2 and ie1, ie2. port1 write operation is accomplished by cycling swck, and holding we1 high after the write address pointer reset operation or rstw1. rstw1 must be preformed for internal circuit initialization before write operation. each write operation, which begins after rstw1, must contain at least 80 active write cycles, i.e. swck cycles while we1 and ie1 are high. to transfer the last data to the dram array, which at that time is stored in the serial data registers attached to the dram array, an rstw1 operation is required after the last swck cycle. note that every write timing of ms8104160 is delayed by one clock compared with read timings for easy cascading without any interface delay devices. setting mode1 to the vss level starts write data accessing in the cycle in which rstw1, we1, and ie1 control signals are input. setting mode1 to the vcc level starts write data accessing in the cycle subsequent to the cycle in which rstw1, we1, and ie1 control signals are input. these operation are the same for port1 and port2. operation mode we1,2 ie1,2 hh hl lx data input internal write address pointer incremented halted x indicates "don't care" not input input settings of we1, 2 and ie1, 2 to the operation mode of write address pointer and data input. write operation cycle (mode2=vcc) the write operation is controlled by seven control signals, swck, rstw1, rstw2, we1, we2, and ie1, ie2. port1 write operation is accomplished by cycling swck and holding both we1 and ie1 low after the write address pointer reset operation or rstw1. rstw1 must be performed for internal circuit initialization before write operation. each write operation, which begins after rstw1, must contain at least 80 active write cycle, i.e. swck cycles while we1 and ie1 are high. to transfer the last data to the dram array, which at that time is stored in the serial data registers attached to the dram array, an rstw1 operation is required after the last swck cycle. note that every write timing of ms8104160 is delayed by one clock compared with read timings for easy cascading without any interface delay devices. setting mode1 to the vss level starts write data accessing in the cycle in which rstw1.we1, and ie1 control signals are input. setting mode1 to the vcc level starts write data accessing in the cycle in which rstw1, we1, and ie1 control signals are input. setting mode1 to the vcc level starts write data accessing in the cycle subsequent to the cycle in which rstw1, we1, and ie1 control signals are input. these operations are the same for port1 and port2.
12 ms81v04160 oki semiconductor read operation cycle (mode2=vss) the read operation is controlled by seven control signals, srck, rstr1, rstr2, re1, re2, and oe1, oe2. port1 read operation is accomplished by cycling srck, and holding both re1 and oe1 high after the read address pointer reset operation or rstr1. each read operation, which begins after rstr1, must contain at least 80 active read cycles, i.e. srck cycles while re1 and oe1 are high. these operations are the same for port1 and port2. re1,2 oe1,2 hh hl lh ll internal write address pointer data output incremented output halted high impedance output high impedance settings of re1, 2 and oe1, 2 to the operation mode of read address pointer and data output. read operation cycle (mode2=vcc) the read operation is controlled by seven control signals, srck, rstr1, rstr2, re1, re2, and oe1, oe2. port1 read operation is accomplished by cycling srck, and holding both re1 and oe1 high after the read address pointer reset operation or rstr1. each read operation, which begins after rstr1, must contain at least 80 active read cycles, i.e. srck cycles while re1 and oe1 are low. these operations are the same for port1 and port2. re1,2 oe1,2 ll lh hl hh halted output high impedance internal write address pointer data output incremented output high impedance settings of re1, 2 and oe1, 2 to the operation mode of read address pointer and data output. settings of we1, 2 and ie1, 2 to the operation mode of write address pointer and data input. we1,2 ie1,2 ll lh hx x indicates "don't care" internal write address pointer data input incremented input not input halted
13 ms81v04160 oki semiconductor old/new data access there must be a minimum delay of 600 swck cycles between writing into memory and reading out from memory. if reading from the first field starts with an rstr1, 2 operation, before the start of writing the second field (before the next rstw1, 2 operation), then the data just written will be read out. the start of reading out the first field of data may be delayed past the beginning of writing in the second field of data for as many as 70 swck cycles. if the rstr1, 2 operation for the first field read-out occurs less than 70 swck cycles after the rstw1, 2 operation for the second field write-in, then the internal buffering of the device assures that the first field will still be read out. the first field of data that is read out while the second field of data is written is called old data. in order to read out new data, i.e., the second field written in, the delay between an rstw1, 2 operation and an rstr1, 2 operation must be at least 600 srck cycles. if the delay between rstw1, 2 and rstr1, 2 operations is more than 71 but less than 600 cycles, then the data read out will be undetermined. it may be old data or new data, or a combination of old and new data. such a timing should be avoided. power-up and initialization on power-up, the device is designed to begin proper operation after at least 100 us after vcc has stabilized to a value within the range of recommended operating conditions. after this 100 us stabilization interval, the following initialization sequence must be performed. because the read and write address pointers are undefined after power-up, a minimum of 80 dummy write operations (swck cycles) and read operations (srck cycles) must be performed, followed by an rstw1, 2 operation and an rstr1, 2 operation, to properly initialize the write and the read address pointer. dummy write cycles/rstw1, 2 and dummy read cycles/rstr1, 2 may occur simultaneously. if these dummy read and write operations start while vcc and/or the substrate voltage has not stabilized, it is necessary to perform an rstr1, 2 operation plus a minimum of 80 srck cycles plus another rstr1,2 operation, and an rstw1,2 operation plus a minimum of 80 swck cycles plus another rstw1,2 operation to properly initialize read and write address pointers.
14 ms81v04160 oki semiconductor timing waveform write cycle timing (write enable) : mode1=vcc , mode2=vss n cycle disable cycle n+1 cycle twenh twwel twens disable cycle twdsh twweh twdss n-1 n n+1 di 10-17/20-27 swck we 1,2 ie 1,2 rstw 1,2 v ih v il v ih v il v ih v il v ih v il v ih v il write cycle timing (write reset) : mode1=vcc , mode2=vss di 10-17/20-27 n cycle 0 cycle 1 cycle 2 cycle tds tdh trstws trstwh twswh twswl tswc n-1 n 0 1 2 swck we 1,2 ie 1,2 rstw 1,2 v ih v il v ih v il v ih v il v ih v il v ih v il
15 ms81v04160 oki semiconductor write cycle timing (input enable) : mode1=vcc , mode2=vss write cycle timing (write reset) : mode1=vcc , mode2=vcc swck ie 1,2 di 10-17/20-27 we 1,2 rstw 1,2 n cycle n+1 cycle n+3 cycle tienh twiel tiens n+2 cycle tidsh twieh tidss n-1 n n+3 v ih v il v ih v il v ih v il v ih v il v ih v il swck rstw 1,2 di 10-27/20-27 we 1,2 ie 1,2 n cycle 0 cycle 1 cycle tds tdh trstws trstwh twswh twswl tswc n-1 n012 2 cycle v ih v il v ih v il v ih v il v ih v il v ih v il
16 ms81v04160 oki semiconductor write cycle timing (write enable) : mode1=vcc , mode2=vcc write cycle timing (input enable) : mode1=vcc , mode2=vcc swck we 1,2 di 10-17/20-27 ie 1,2 rstw1,2 twenh twwel twens v ih v il v ih v il v ih v il v ih v il twdsh twweh twdss v ih v il n-1 n n+1 n cycle disable cycle n+1 cycle disable cycle swck ie 1,2 we 1,2 rstw 1,2 n cycle n+1 cycle n+3 cycle tienh twiel tiens v ih v il v ih v il v ih v il v ih n+2 cycle tidsh twieh tidss di 10-17/20-27 v ih v il n-1 n n+3 v il
17 ms81v04160 oki semiconductor write cycle timing (write reset) : mode1=vss , mode2=vss write cycle timing (write enable) : mode1=vss , mode2=vss swck rstw 1,2 di 10-17/20-27 we 1,2 ie 1,2 n cycle 0 cycle 1 cycle 2 cycle tds tdh n0123 v ih v il v ih v il v ih v il v ih v il v ih v il trstws trstwh twswh twswl tswc swck we 1,2 di 10-17/20-27 ie 1,2 rstw 1,2 n cycle disable cycle n+1 cycle twenh twwel twens disable cycle twdsh twweh twdss nn+1n v ih v il v ih v il v ih v il v ih v il v ih v il
18 ms81v04160 oki semiconductor write cycle timing (input enable) : mode1=vss , mode2=vss write cycle timing (write reset) : mode1=vss , mode2=vcc swck ie 1,2 di 10-17/20-27 we 1,2 rstw 1,2 n cycle n+1 cycle n+3 cycle tienh twiel tiens n+2 cycle tidsh twieh tidss nn n+4 v ih v il v ih v il v ih v il v ih v il v ih v il n+3 swck rstw 1,2 di 10-27/20-27 we 1,2 ie 1,2 n cycle 0 cycle 1 cycle tds tdh trstws trstwh twswh twswl tswc n-1 n 0 1 2 2 cycle v ih v il v ih v il v ih v il v ih v il v ih v il n-1 cycle
19 ms81v04160 oki semiconductor write cycle timing (write enable) : mode1=vss , mode2=vcc write cycle timing (input enable) : mode1=vss , mode2=vcc swck we 1,2 di 10-17/20-27 ie 1,2 rstw1,2 twenh twwel twens v ih v il v ih v il v ih v il v ih v il twdsh twweh twdss v ih v il n n+1 n+2 n cycle disable cycle n+1 cycle disable cycle n+2 cycle swck ie 1,2 we 1,2 rstw 1,2 n cycle n+1 cycle n+3 cycle tienh twiel tiens v ih v il v ih v il v ih v il v ih n+2 cycle tidsh twieh tidss di 10-17/20-27 v ih v il n n+3 n+4 v il
20 ms81v04160 oki semiconductor read cycle timing (read reset) : mode1=vcc/vss , mode2=vss do 10-17/20-27 srck rstr 1,2 re 1,2 oe 1,2 n cycle 0 cycle 1 cycle 2 cycle tac trstrs trstrh twsrh twsrl tsrc v ih v il v ih v il v oh v ol v ih v il v ih v il n-1 n 0 1 2 tddck read cycle timing (read enable) : mode1=vcc/vss , mode2=vss srck re 1,2 do 10-17/20-27 oe 1,2 rstr 1,2 n cycle disable cycle n+1 cycle trenh twrel trens v ih v il v ih v il v oh v ol v ih v il v ih v il disable cycle trdsh twreh trdss n-1 n n+1
21 ms81v04160 oki semiconductor read cycle timing (output enable) : mode1=vcc/vss , mode2=vss srck oe 1,2 do 10-17/20-27 re 1,2 rstr 1,2 n cycle n+1 cycle n+3 cycle toenh twoel toens v ih v il v ih v il v oh v ol v ih v il v ih v il n+2 cycle todsh twoeh todss n-1 n n+3 hi-z tdeck read cycle timing (read reset) : mode1=vcc/vss , mode2=vcc srck rstr 1,2 do 10-17/20-27 re 1,2 oe 1,2 n cycle 1 cycle 2 cycle tac trstrs trstrh twsrh twsrl tsrc v ih v il v ih v il v oh v ol v ih v il v ih v il n-1 n 12 0 cycle 0 tdeck
22 ms81v04160 oki semiconductor read cycle timing (read enable) : mode1=vcc/vss , mode2=vcc rstr 1,2 v srck re 1,2 do 10-17/20-27 oe 1,2 n cycle disable cycle n+1 cycle trenh twrel trens disable cycle trdsh twreh trdss n-1 n n+1 tac v ih v il v ih v il v oh v ol v ih v il v ih il read cycle timing (output enable) : mode1=vcc/vss , mode2=vcc srck toenh todsh todss oe 1,2 do 10-17/20-27 re 1,2 rstr 1,2 n cycle n+1 cycle n+3 cycle twoel toens n+2 cycle twoeh n-1 n n+3 hi-z v ih v il v ih v il v oh v ol v ih v il v ih v il

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